The quest for visual rehabilitation via retinal implant technology remains a complex, multi-dimensional endeavor. Retinal implants are biomedical devices surgically introduced into the ocular region. They propose a novel treatment for degenerative retinal pathologies. One of the most challenging aspects is replicating the retina’s natural scene encoding. Many investigative teams have consistently pursued strategies to overcome this intricate challenge. Still, no one has effectively generated a device mirroring 20/20 vision. This paper presents a proof-of-concept framework that models the computational circuitry of the human retina using spiking neural networks (SNNs) and implements the model on a mixed-signal application-specific integrated circuit (ASIC) employing leaky integrate-and-fire (LIF) neurons. The proposed neuromorphic system on chip (NeuroSoC) demonstrates energy and area efficiency, achieving an energy consumption of approximately 25 pJ per synaptic operation and operating within an active silicon area of about 1 mm square. A detailed characterization of the chip is provided, including measurements of energy consumption per inference, an inference time of 1.264 ms, and validation over process, voltage, and temperature variations. Additionally, a Python-based emulation framework derived from chip measurements is developed and integrated with machine learning techniques, yielding a post-training quantization accuracy of 80.3% over 4-bit resolution on a synthetic retinal dataset modeled after Parasol ON retinal ganglion cells using the CIFAR-10 dataset. These quantitative performance metrics underscore the effectiveness and impact of our approach for potential retinal implant applications.

An ultrasound (US) phased array with electronic steering and focusing capability can enable high-resolution, large-scale US interventions in various medical research and clinical experiments. For such applications involving different animal subjects and humans, the phased array system must provide flexibility in generating waveforms with different patterns (including experimental parameters), precise delay resolution between channels, and high voltage across US transducers to produce high US pressure output over extended durations. This paper presents a 16-channel high-voltage phased array system designed for therapeutic medical applications, capable of driving US transducers with pulses up to 100 V and a fine delay resolution of 5 ns, while providing a wide range of sonication waveforms. The modular 16-channel electronics are integrated with a custom-built, 2 MHz, 16-element US transducer array with dimensions of 4.3×11.7×0.7 mm³. In measurements, the phased array system achieved a peak-to-peak US pressure output of up to 6 MPa at a focal depth of 10 mm, with lateral and axial resolution of 0.6 mm and 4.67 mm, respectively. Additionally, the beam focusing and steering capability of the system in measurements and the theoretical analysis of the power consumption of the high-voltage driver (along with measured results) are provided. Finally, the phased array system’s ability to steer and focus the ultrasound beam for blood-brain barrier (BBB) opening in different brain regions is successfully demonstrated in vivo.

This paper presents the design of a high-voltage 8-channel neural stimulation integrated circuit with exponential-waveform output. To ensure sufficient current delivery to the load, which exhibits large impedance at the electrode-tissue interface, a high-voltage output stage of up to 30 V has been implemented in the neural stimulator. Charge balancing is achieved through a dual-slope control scheme with an integrator circuit during stimulation, complemented by an additional active charge-balancing circuit in each channel. This work also demonstrates that the stimulator with exponential-waveform output remains effective even with a high-voltage output stage and is compatible with traditional charge-balancing circuits. These features ensure safety and higher power efficiency in long-term stimulation. The 8-channel high-voltage stimulator chip is implemented using 180-nm BCD CMOS process technology, with a core area of 13.25 mm². Experimental measurements indicate that the maximum charge imbalance for a single cycle is only 0.77%, while the output power efficiency can reach 98%. In vitro and in vivo experimental results show that the stimulator effectively removes residual charges, and the exponential-waveform stimulation successfully triggers action potentials leading to muscle contraction.